Maxeler chairman claims ‘200 fold’ seismic speedup

Mike Flynn claims that Field Programmable Gate Array technology beats CPU hands-down.

Mike Flynn, professor of electrical engineering at Stanford university and chairman of Maxeler Technologies, speaking at a seminar at Stanford this month, claimed that FPGA* technology ‘wins out on performance’ for most applications. Flynn believes that Maxeler’s FPGA compiler toolkit now makes it possible to transform an application into a data flow graph that can be mapped to an ‘unconstrained systolic array.’ This allows the array structure to be matched to the applications structure without the constraint of nearest neighbor communications. Flynn has mapped a forward modeling seismic imaging algorithm to a 2,000 node systolic array on 2 FPGAs. Each node performs an operation every 4 nanoseconds, resulting in a 200 fold speedup ‘compared to an Intel CPU.’ More from

* Field programmable gate arrays.

This article originally appeared in Oil IT Journal 2009 Issue # 5.

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